Datasheet

MOTOROLA MCF5206e USER’S MANUAL 11-1
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SECTION 11
DRAM CONTROLLER
11.1 INTRODUCTION
The DRAM controller (DRAMC) provides a glueless interface between the ColdFire
®
core
and external DRAM. The DRAMC supports two banks of DRAM. Each DRAM bank can be
from 128 KByte to 256 MByte. The DRAMC can support DRAM bank widths of 8, 16, or 32
bits. Two row address strobe (RAS[1:0]) signals are provided externally to access the two
DRAM banks. Data byte lanes are enabled using the four column address strobe (CAS
[3:0])
signals. The DRAM write (DRAMW
) signal indicates if the DRAM transfer is a read or a write.
The DRAMC handles address multiplexing internally, allowing for a glueless DRAM
interface. The DRAMC has an internal refresh timer that generates CAS-before-RAS refresh
cycles. You can program RAS and CAS waveform timing and refresh rates. External master
use of the DRAMC for accessing the DRAM banks is also supported.
11.1.1 Features
The following list summarizes the key DRAMC features:
• Supports two banks of DRAM
• Supports Normal Mode, Fast Page Mode, and Burst Page Mode
• Supports EDO DRAMs
• Supports glueless row address/column address multiplexing
• Programmable RAS and CAS timings
• Programmable refresh timer for CAS-before-RAS refresh
• Supports external master use of the DRAMC
11.2 DRAM CONTROLLER I/O
11.2.1 Control Signals
The DRAMC has seven control signal signals: CAS[0], CAS[1], CAS[2], CAS[3], RAS[0],
RAS
[1], and DRAMW.
11.2.1.1 ROW ADDRESS STROBES (RAS
[0], RAS[1]). These active-low output signals
provide control for the row address strobe (RAS) input pins on industry-standard DRAMs.
There is one RAS
output for each DRAM bank: RAS[0] controls DRAM bank 0 and RAS[1]
controls DRAM bank 1. RAS
timing can be customized to match the specifications of the
DRAM being used by programming the DRAMC Timing Register (see Section 11.4.2.2
DRAM Controller Timing Register (DCTR)).
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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