Datasheet

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DRAM Controller
11-2 MCF5206e USER’S MANUAL MOTOROLA
11.2.1.2 COLUMN ADDRESS STROBES (CAS[0], CAS[1], CAS[2], CAS[3]). These
active-low output signals provide control for the column address strobe (CAS) input pins
on industry-standard DRAMs. The CAS signals are used to enable data byte lanes:
CAS[0] controls access to D[31:24], CAS[1] to D[23:16], CAS[2] to D[15:8], and CAS[3] to
D[7:0]. CAS[3:0] should be used for a 32-bit wide DRAM bank, CAS[1:0] for a 16-bit wide
DRAM bank, and CAS[0] for an 8-bit wide DRAM bank. Table 11-1 shows which CAS
signals are asserted based on the operand size, the DRAM port size and the address bits
A[1:0]. For DRAM transfers SIZ[1:0] always matches the operand size.
Table 11-1. CAS Assertion
OPERAND SIZE PORT SIZE SIZ[1] SIZ[0] A[1] A[0]
CAS
[0] CAS[1] CAS[2] CAS[3]
D[31:24] D[23:16] D[15:8] D[7:0]
BYTE
8-BIT 0 1
000111
010111
100111
110111
16-BIT 0 1
000111
011011
100111
111011
32-BIT 0 1
000111
011011
101101
111110
WORD
8-BIT 1 0
000111
010111
100111
110111
16-BIT 1 0
000011
100011
32-BIT 1 0
000011
101100
LONGWORD
8-BIT 0 0
000111
010111
100111
110111
16-BIT 0 0
000011
100011
32-BIT00000000
Fr
eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
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