Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-3
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CAS timing can be customized to match the specifications of the DRAM by programming
the DRAM Controller Timing Register (see Section 11.4.2.2 DRAM Controller Timing
Register (DCTR)).
11.2.1.3 DRAM WRITE (DRAMW). This active-low output signal is asserted during
DRAM write cycles, and negated during DRAM read cycles. The DRAMW signal is
negated during refresh cycles.The DRAMW signal is provided in addition to the R/W
signal to allow refreshes to occur during nonDRAM cycles (regardless of the state of the
R/W signal). The R/W signal indicates the direction of all bus transfers, while DRAMW is
only valid during DRAM transfers.
11.2.2 Address Bus
The address bus includes 24 dedicated address signals, A[23:0], and supports as many
as four additional configurable address signals, A[27:24] (refer to Section 7.3.2.10 Pin
Assignment Register (PAR)). The DRAM address appears only on the pins configured
to be address signals. The maximum size of DRAM that can be connected to each bank
is limited by the number of address signals available (see Table 11-2).
For transfers initiated by the ColdFire core, the DRAMC outputs both the row address and
the column address, allowing the address bus to be directly connected to external DRAM.
The internal address multiplexing can be selectively enabled for transfers initiated by an
external master by programming the DAEM bit in the DCTR (see Section 11.4.2.2 DRAM
Controller Timing Register (DCTR)).
LINE
8-BIT 1 1
000111
010111
100111
110111
16-BIT 1 1
000011
100011
32-BIT11000000
Table 11-2. Maximum DRAM Bank Sizes
AVAILABLE
ADDRESS
SIGNALS
MAXIMUM DRAM
SIZE
A[23:0] 16 MBytes
A[24:0] 32 MBytes
A[25:0] 64 MBytes
A[26:0] 128 MBytes
A[27:0] 256 MBytes
Table 11-1. CAS Assertion (Continued)
OPERAND SIZE PORT SIZE SIZ[1] SIZ[0] A[1] A[0]
CAS
[0] CAS[1] CAS[2] CAS[3]
D[31:24] D[23:16] D[15:8] D[7:0]
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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