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DRAM Controller
11-4 MCF5206e USER’S MANUAL MOTOROLA
11.2.3 Data Bus
The DRAM banks can be configured to be 8, 16, or a 32-bits wide. A 32-bit port must
reside on data bus bits D[31:0], a 16-bit port must reside on data bus bits D[31:16] and an
8-bit port must reside on data bus bits D[31:24]. This requirement ensures that the
MCF5206e correctly transfers valid data to 8, 16 and 32-bit ports. Figure 11-1 illustrates
the connection of the data bus to 8-, 16-, and 32-bit ports.
Figure 11-1. MCF5206e Interface to Various Port Sizes
11.3 DRAM CONTROLLER OPERATION
The DRAMC provides a glueless interface to industry-standard DRAMs. The following
sections describe the reset operation, definition of DRAM banks, normal mode, Fast Page
Mode, burst page mode, Extended Data-Out DRAM support, refresh operation, and
external master operation.
NOTE
All timing diagrams in the following sections illustrate the
fastest possible waveform timing; however, in all cases, the
DRAM Controller Timing Register (DCTR) can be
programmed to generate slower waveform timing.
11.3.1 Reset Operation
The MCF5206e supports two types of external hardware reset—Master Reset and
Normal Reset. Master Reset resets the entire MCF5206e including all functions of the
DRAMC. Normal Reset resets all of the functions of the MCF5206e with the exception of
the DRAMC Refresh Controller. During Normal Resets, the Refresh Controller continues
to generate refresh cycles at the programmed rate and with the programmed cycle timing.
EXTERNAL
DATA BUS
BYTE 0
8-BIT PORT
16-BIT PORT
32-BIT PORT
BYTE 1
BYTE 2
BYTE 3
BYTE 0 BYTE 1
BYTE 2 BYTE 3
BYTE 0 BYTE 1 BYTE 2 BYTE 3
D[31:24] D[23:16] D[15:8] D[7:0]
Fr
eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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