Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-5
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NOTE
Master Reset must be asserted for all power-on resets. Failure
to assert Master Reset on power-on reset could result in
unpredictable DRAMC behavior.
11.3.1.1 MASTER RESET. During a master reset all registers in the DRAMC are
initialized to a known state and all DRAMC operation is halted. The DRAM refresh counter
does not count and DRAM refresh cycles are not generated. Any DRAM transfer or
refresh cycle in progress is immediately terminated.
A master reset is accomplished by asserting and negating the RSTI and HIZ signals
simultaneously, these signals are both synchronized (with setup) to the falling edge of
CLK (see Section 6.11 reset Operation).
NOTE
During a master reset, the DCCR is reset to $000 (giving the
slowest refresh rate) and the DCTR is reset to $0000 (giving
the fastest waveform timing). After a Master Reset, the user
should program the DRAMC Refresh Register (DCRR) and
the DRAMC Timing Register (DCTR) such that refresh cycles
are generated at the required rate and with the required timing
for the DRAM in the system. In general, DRAMs require an
initial pause after power-up and require a minimum number of
DRAM cycles to be run before the DRAM is ready for use. This
“wake-up” sequence must be handled via software.
11.3.1.2 NORMAL RESET. Normal reset is used when the DRAM contains valid data
which needs to be maintained through reset. The DRAMC Refresh Register (DCRR),
DRAMC Timing Register (DCTR), and the internal DRAMC Refresh controller are
unaffected by normal reset. All other MCF5206e registers are reset to the same values
during normal resets as during Master Resets. During normal reset, DRAM refreshes
occurs at the programmed rate and with the programmed DRAM cycle timing.
A normal reset is accomplished by asserting the RSTI
signal while negating the HIZ
signal. Resets generated by the internal software watchdog timer are normal resets.
11.3.2 Definition of DRAM Banks
The DRAMC supports as many as two banks of DRAM. You can program each bank
independently except for the RAS and CAS waveform timing (programming the DCTR
affects the waveform timing for both banks).
11.3.2.1 BASE ADDRESS AND ADDRESS MASKING. The transfer address generated
by the ColdFire core or by an external master is compared to the unmasked bits of the
base address programmed for each bank in the DRAMC Address Registers (DCAR0 -
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Freescale Semiconductor, Inc.
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