Datasheet

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DRAM Controller
11-6 MCF5206e USER’S MANUAL MOTOROLA
DCAR1). The bits that are masked is determined by the value programmed in the BAM
field in the DRAMC Mask Registers (DCMR0 - DCMR1).
The masking of address bits is used to define the address space of the DRAM bank.
Address bits that are masked are not used in the comparison with the transfer address.
The base address field (BA31-BA17) in the DCARs and the base address mask field
(BAM31-BAM17) in the DCMRs correspond to transfer address bits 31-17. Clearing
(unmasking) all bits in the BAM field makes the address space 128 KBytes. For the
address space of a DRAM bank to be contiguous, address bits should be masked (BAM
bits set to a 1) in ascending order starting with A[17].
For example, if the DCARs and DCMRs are programmed as shown in Table 11-3, DRAM
bank 0 would have a 16 MByte address space starting at address $04000000, while
DRAM bank 1 would have a 1 MByte address space starting at address $05000000. A
transfer with A[31:24] = $04 accesses DRAM bank 0, and a transfer address with A[31:20]
= $050 accesses DRAM bank 1.
Refer to Section 11.4.2.3 DRAM Controller Address Register (DCAR0 - DCAR1) and
Section 11.4.2.4 DRAM Controller Mask Register (DCMR0 - DCMR1) for further
details.
NOTE
The ColdFire core outputs 32 bits of address to the internal
bus controller. Of these 32 bits, only A[27:0] are output to pins
on the MCF5206e. The output of A[27:24] are dependent on
the setting of PAR3-PAR0 in the Pin Assignment Register
(PAR) in the SIM.
NOTE
The MCF5206e compares the address for the current bus
transfer with the address and mask bits in the Chip Select
Address Registers (CSARs), DRAM Controller Address
Registers (DCARs) and the Chip Select Mask Registers
(CSMRs) and DRAM Controller Mask Register (DCMRs),
Table 11-3. DRAM Bank Programming Example 1
DRAM BANK DCAR DCMR
DRAM ADDRESS
SPACE
ADDRESS MATCH
0 $0400 $00FE0000 16 Mbyte $04xxxxxx
1 $0500 $000E0000 1 Mbyte $050xxxxx
Fr
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Freescale Semiconductor, Inc.
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