Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-7
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looking for a match. The priority is listed in Table 11-4 (from
highest priority to lowest priority):
The MCF5206e compares the address and mask in chip
select 0 - 7 (chip select 0 is compared first), then the address
and mask in DRAM 0 - 1. If the address does not match in
either or these, the MCF5206e uses the control bits in the
Default Memory Control Register (DMCR) to control the bus
transfer. If the Default Memory Control Register (DMCR)
control bits are used, no chip select or DRAM control signals
are asserted during the transfer.
11.3.2.2 ACCESS PERMISSIONS. DRAM bank accesses can be restricted based on
transfer direction and attributes. Each DRAM bank can be enabled for read and/or write
transfers using the WR and RD bits in the DCCRs. Each DRAM bank can have supervisor
data, supervisor code, user data, and user code transfers masked from their address
space using the SD, SC, UD, and UC bits in the DCMRs. The transfer address must
match, the transfer direction must be enabled, and transfer attributes must be unmasked
for a transfer to a DRAM bank to occur.
For example, if the DCARs, DCMRs, and DCCRs are programmed as shown in Table 11-
5, DRAM bank 0 would start at address $04000000, and be 16 MBytes, read/write, and
available for supervisor transfers only. DRAM bank 1 would start at address $05000000
and be 1 MBytes, read-only, and available to all address spaces.
If a user data read transfer was attempted to address $04000000, the transfer would not
access DRAM bank 0, because user space transfers are masked. The transfer would not
access DRAM bank 1 because the addresses do not match. Therefore, a Default Memory
transfer would occur.
If a user data write transfer was attempted to address $05000000, the transfer would not
access DRAM bank 0 because the addresses do not match. The transfer would not
access DRAM bank 1 because this bank is not enabled for writes. Therefore, a Default
Memory transfer would occur.
Table 11-4. Chip Select, DRAM and Default Memory Address Decoding Priority
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
DRAM Bank 0
DrRAM Bank 1
Default Memory
Highest priority
Lowest priority
Fr
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Freescale Semiconductor, Inc.
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