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DRAM Controller
11-8 MCF5206e USER’S MANUAL MOTOROLA
Refer to Section 11.4.2.4 DRAM Controller Mask Register (DRMR0 - DCMR1) and
Section 11.4.2.5 DRAM Controller Control Register (DCCR0 - DCCR1) for further
details.
11.3.2.3 TIMING. The timing of RAS and CAS assertion and negation can be customized
to meet the timing specifications for the specific DRAM being used. This programmed
waveform timing is used for both banks. Refer to Section 11.4.2.2 DRAM Controller
Timer Register (DCTR) for further details.
11.3.2.4 PAGE MODE. Each bank can be configured for normal mode, fast page mode,
or burst page mode. Normal mode DRAM cycles supply a row address and a column
address for each transfer. Fast page mode DRAM cycles supply a row address and a
column address for the first transfer to a page and only a column address on successive
transfers to that page. Burst page mode is a combination of normal mode and fast page
mode. For transfers where the port size is larger or the same as the operand size (non-
burst transfers), burst page mode operates the same as normal mode. For transfers
where the operand size is larger than the port size (burst transfers), burst page mode
operates the same as fast page mode. Refer to 11.3.3 Normal Mode Operation, 11.3.4
Fast Page Mode Operation, 11.3.5 Burst Page Mode Operation, and Section 11.4.2.5
DRAM Controller Control Register (DCCR0 - DCCR1) for further details.
11.3.2.5 PORT SIZE/PAGE SIZE. Each DRAM bank can be programmed for 8-, 16-, or
32-bit port sizes. Each bank can also have an internal bank page size of 512 byte, 1 kbyte,
or 2 kbyte. Refer to Section 11.4.2.5 DRAM Controller Control Register (DCCR0 -
DCCR1) for further details.
11.3.2.6 ADDRESS MULTIPLEXING. The MCF5206e provides internal address
multiplexing of the row address and column address for DRAM transfers. The internal
address multiplexing is used for all ColdFire core initiated DRAM transfers and can
selectively be used for external master initiated DRAM transfers. No external logic is
required in the system to handle DRAM address multiplexing when the internal
multiplexing is used. In addition, the multiplexing scheme allows a single printed circuit
board layout to support multiple DRAM memory sizes (allowing for easy memory
upgrades).
A subset of the address pins should be connected directly to the address inputs of the
DRAM to supply the row address and column address. The DRAM port size and bank
page size determine which address pins should be connected to the address inputs of the
DRAM. In Figure 11-2, the address multiplexing scheme is illustrated for an 8-bit DRAM
with 9 address inputs using a 512 byte page size (PS=01 and BPS=00 in the DCCR). In
this case, the DRAM address inputs (DA[x]) would be connected to the MCF5206e
Table 11-5. DRAM Bank Programming Example 2
DRAM BANK DCAR DCMR DCCR ADDRESS MATCH TRANSFER TYPE READ/WRITE
0 $0400 $00FE0006 $03 $04xxxxxx supervisor-only read/write
1 $0500 $000E0000 $01 $050xxxxx all transfer types read-only
Fr
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Freescale Semiconductor, Inc.
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