Datasheet

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
DRAM Controller
11-10 MCF5206e USER’S MANUAL MOTOROLA
size (BPS). The shaded address pins in each PS/BPS configuration outputs the row
address during the assertion of RAS and the column address during the assertion of CAS.
These signals should be connected to the DRAM address inputs. The number of address
signals used depends on the size of the DRAM. Because byte CAS signals (CAS[3:0]) are
provided, A[0] is unnecessary for 16-bit DRAMs and A[1:0] are unnecessary for 32-bit
DRAMs.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...