Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-15
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For the 4 M x 8 DRAM, the DCCR and DCMR would be programmed as follows:
DCCR: $57 (port size = 8 bits, page size = 1KByte, burst page mode, read/write)
DCMR: $001E0000 (A[20:17] are masked => 4 MByte)
Figure 11-3. Diagram for 4 MByte DRAM with 8 bit Port and 1 KByte Page
For the 1 M x 8 DRAM, the DCCR and DCMR would be programmed as follows:
DCCR: $57 (port size = 8 bits, page size = 1KByte, burst page mode, read/write)
DCMR: $000E0000 (A[19:17] are masked => 1 MByte).
Figure 11-4. Diagram for 1 MByte DRAM with 8 Bit Port and 1 KByte Page
11.3.3 Normal Mode Operation
Normal mode is the simplest form of DRAM transfer. In this mode, row addresses and
column addresses are supplied for every transfer. For DRAM transfers initiated by the
ColdFire core that access a bank programmed for normal mode, the MCF5206e supplies
a row address on the address bus, drives DRAMW to indicate whether a read or a write
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
RAS
CAS
WE
D[7:0]
A[21]
A[19]
A[18]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
RAS
[0]
CAS
[0]
DRAMW
D[31:24]
4M x 8
DRAM
MCF5206e
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
RAS
CAS
WE
D[7:0]
A[19]
A[18]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
RAS
[0]
CAS
[0]
DRAMW
D[31:24]
1M x 8
DRAM
MCF5206e
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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