Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-17
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Figure 11-5. Byte Read Transfers in Normal Mode with 8-bit DRAM
Clock H1
The first DRAM-read transfer starts in H1. During H1, the MCF5206e drives the row
address on the A[27:9], drives DRAMW high indicating a DRAM read transfer, drives
SIZ[1:0] to $1 indicating a byte transfer, and asserts TS.
Clock L1
The MCF5206e asserts RAS to indicate the row address is valid on the address bus.
Clock H2
The MCF5206e negates TS and drives the column address on the address bus.
Clock L2
The MCF5206e asserts CAS
[0] to indicate the column address is valid on the address
bus. At this point, the DRAM turns on its output drivers and begins driving data on
D[31:24].
CLK
A[27:9]
RAS
CAS[0]
DRAMW
D[31:24]
TS
INTERNAL TA
ROW COL
COL
ROW
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8 H9
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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