Datasheet

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DRAM Controller
11-18 MCF5206e USER’S MANUAL MOTOROLA
Clock H3
The internal transfer acknowledge asserts to indicate that the current transfer is
completed and the data on the D[31:24] will be registered on the next rising edge of CLK.
Clock H4
The MCF5206e registers the read data driven by the DRAM and negates the internal
transfer acknowledge, RAS and CAS[0], ending the first byte-read transfer. This begins
the RAS precharge. Once CAS[0] is negated, the DRAM disables its output drivers, and
the data bus is three-stated.
Clock H6
Clock H6 is the earliest the next transfer initiated by the ColdFire core can start. The
second DRAM byte-read transfer starts in H6. During H6, the MCF5206e drives the row
address on the A[27:9], drives DRAMW high indicating a DRAM-read transfer, drives
SIZ[1:0] to $1 indicating a byte transfer, and asserts TS.
Clock L6
The MCF5206e asserts RAS to indicate the row address is valid on the address bus.
Clock H7
The MCF5206e negates TS and drives the column address on the address bus.
Clock L7
The MCF5206e asserts CAS[0] to indicate the column address is valid on the address
bus. At this point, the DRAM turns on its output drivers and begins driving data on
D[31:24].
Clock H8
The internal transfer acknowledge asserts to indicate that the current transfer will be
completed and the data on the D[31:24] will be registered on the next rising edge of CLK.
Clock H9
The MCF5206e registers the read data driven by the DRAM and negates the internal
transfer acknowledge, RAS and CAS[0], ending the first byte-read transfer. This begins
the RAS precharge. Once CAS[0] is negated, the DRAM disables its output drivers, and
the data bus is three-stated.
11.3.3.2 BURST TRANSFER IN NORMAL MODE. A burst transfer to DRAM is
generated when the operand size is larger than the DRAM bank port size (e.g., line
transfer to a 32-bit port, longword transfer to an 8-bit port). On all DRAM transfers, the
Fr
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Freescale Semiconductor, Inc.
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