Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-19
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MCF5206e asserts TS only once. The start of the secondary transfers of a burst is delayed
by the DRAMC until the programmed RAS precharge time is reached.
The timing of burst reads and burst writes is identical in normal page mode, with the
exception of when the DRAM drives data on reads and when the MCF5206e drives data
on writes.
The fastest possible burst transfer in normal mode requires 3 clocks for the first transfer
of the burst and 4 clocks for the secondary transfers (including a 1.5 clock RAS precharge
time). You can program the DCTR to generate slower normal mode transfers.
Figure 11-6 shows the timing of a burst longword write transfer to a 16-bit port in normal
mode.
Figure 11-6. Longword Write Transfer in Normal Mode with 16-bit DRAM
Clock H1
The first DRAM write transfer of the burst starts in H1. During H1, the MCF5206e drives
the row address on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives
SIZ[1:0] to $0 indicating a longword transfer, and asserts TS. The address driven on the
A[27:9] corresponds to the DRAM row address for the first transfer of the burst.
Clock L1
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
CLK
A[27:9]
RAS
CAS[1:0]
DRAMW
D[31:16]
TS
INTERNAL TA
ROW COL COLROW
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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