Datasheet

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DRAM Controller
11-20 MCF5206e USER’S MANUAL MOTOROLA
Clock H2
The MCF5206e negates TS, drives the column address on A[27:9], and begins driving the
data on D[31:16] for the first word write of the longword burst.
Clock L2
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on the A[27:9].
Clock H3
The internal transfer acknowledge asserts to indicate the first word transfer of the
longword burst will be completed on the next rising edge of CLK.
Clock H4
The MCF5206e negates the internal transfer acknowledge, RAS and CAS[1:0], ending
the first word write transfer of the longword burst. This begins the RAS precharge. The
MCF5206e drives the row address on A[27:9], and begins driving the data on D[31:16] for
the second word write of the longword burst.
Clock L4/H5
The MCF5206e continues to negate RAS to meet the precharge time.
Clock L5
After the RAS precharge time is reached, the MCF5206e asserts RAS to indicate the row
address is valid on A[27:9].
Clock H6
The MCF5206e drives the column address on A[27:9].
Clock L6
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9].
Clock H7
The internal transfer acknowledge asserts to indicate the first word transfer of the
longword burst will be completed on the next rising edge of CLK.
Clock H8
The MCF5206e negates the internal transfer acknowledge, RAS and CAS[1:0], ending
the second word write transfer of the longword burst. This begins the RAS precharge.
When the burst write is completed, D[31:0] is three-stated.
Fr
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Freescale Semiconductor, Inc.
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