Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-21
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11.3.4 Fast Page Mode Operation
Fast page mode operation allows faster successive transfers to locations in DRAM that
have the same row address. All locations with the same row address are said to be on the
same “page.” Successive transfers that have the same row address as the initial transfer
are called “page hits,” while successive transfers with different row addresses are called
“page misses.”
On the initial transfer to a page, the DRAMC stores the row address. The address of a
successive transfer is compared with the stored row address to determine if the transfer
is a page hit or a page miss. For a page size of 512 Bytes (BPS=$0 in the DCTR), bits 31-
9 of the transfer address must match the corresponding bits stored as the active row
address to be a page hit. For a page size of 1 KByte (BPS=$1), bits 31-10 of the transfer
address must match the corresponding bits of the active row address to be a page hit. For
a page size of 2 KBytes (BPS=$2), bits 31-11 of the transfer address must match the
corresponding bits of the active row address to be a page hit.
Fast page mode transfers are facilitated by having the RAS signal remain asserted while
asserting CAS to access successive column locations determined by the column address.
Once RAS asserts on a transfer to a page, the page is said to be “open” and RAS remains
asserted on all successive transfers to that page. If a transfer to a location in the current
DRAM bank is a page hit, only the column address is driven and CAS asserted.
In fast page mode, RAS negates (precharge), “closing” the current page, under the
following conditions:
1. A transfer occurs to an address in the current DRAM bank that is a page miss
2. A transfer occurs to an address in the other DRAM bank
3. The MCF5206e loses bus mastership
4. A refresh cycle is pending
In each of these cases, the RAS negates and the DRAMC does not allow an access to
that bank until the RAS
precharge time is met.
11.3.4.1 BURST TRANSFER IN FAST PAGE MODE. A burst transfer to DRAM is
generated when the operand size is larger than the DRAM bank port size (e.g., line
transfer to a 32-bit port, longword transfer to an 8-bit port). Burst transfers can access from
two to 16 segments of data in a single transfer. On all DRAM transfers the MCF5206e
asserts TS only once. The internal TA is asserted to indicate the transfer of each segment
of data. The start of the secondary transfers of a burst are delayed by the DRAMC until
the programmed RAS
precharge time is reached.
The timing of burst reads and burst writes is identical in fast page mode, with the exception
of when the DRAM drives data on reads and when the MCF5206e drives data on writes.
The fastest possible burst transfer in normal mode takes 3 clocks for the initial transfer, 2
clocks for secondary transfers with a 0.5 clock CAS precharge time and a 1.5 clock RAS
precharge time. You can program the DCTR to generate slower fast page mode transfers.
Fr
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Freescale Semiconductor, Inc.
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