Datasheet

LIST OF TABLES (Continued)
Figure Page
Number Title Number
xxviii MCF5206e USER’S MANUAL MOTOROLA
5-1. Memory Map of SIM Registers ....................................................................... 5-2
5-2. Examples of Typical RAMBAR Settings ......................................................... 5-4
6-1. SIZx Encoding................................................................................................. 6-2
6-2. Transfer Type Encoding.................................................................................. 6-3
6-3. ATM Encoding ................................................................................................ 6-3
6-4. Chip Select, DRAM and Default Memory Address Decoding Priority............. 6-7
6-5. SIZx Encoding for Burst- and Bursting-Inhibited Ports ................................... 6-9
6-6. Address Offset Encoding ................................................................................ 6-9
6-7. Data Bus Requirement for Read Cycles...................................................... 6-10
6-8. Internal to External Data Bus Multiplexer - Write Cycle................................ 6-13
6-9. SIZx Encoding for Burst- and Bursting-Inhibited Ports ................................. 6-19
6-10. MCF5206e Two-Wire Bus Arbitration Protocol Transition Conditions .......... 6-59
6-11. MCF5206e Two-Wire Arbitration Protocol State Diagram ............................ 6-60
6-12. MCF5206e Three-Wire Bus Arbitration Protocol Transition Conditions....... 6-65
6-13. MCF5206e Three-Wire Arbitration Protocol State Diagram.......................... 6-66
6-14. Signal Source During Alternate Master Accesses ........................................ 6-69
7-1. DMA Signals ....................................................................................................7-3
7-2. DMA Controller Module Channel Offsets.........................................................7-6
7-3. BWC Encoding ................................................................................................7-9
7-4. SSIZE Encoding............................................................................................ 7-10
7-5. DSIZE Encoding ........................................................................................... 7-10
8-1. Interrupt Levels for Encoded External Interrupts ............................................ 8-4
8-2. Memory Map of SIM Registers ....................................................................... 8-7
8-3. Interrupt Control Register Assignments........................................................ 8-10
8-4. Interrupt Mask Register Bit Assignments..................................................... 8-11
8-5. Interrupt Pending Register Bit Assignments ................................................ 8-12
8-6. SWT Timeout Period..................................................................................... 8-15
8-7. Bus Monitor Timeout Periods........................................................................ 8-15
8-8. PAR3 - PAR0 Pin Assignment..................................................................... 8-17
8-9. Arbitration Control Encodings (ARBCTRL)....................................................8-19
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eescale S
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