Datasheet

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DRAM Controller
11-22 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-7 shows the timing of a word write transfer to an 8-bit port in fast page mode.
Figure 11-7. Word Write Transfer in Fast Page Mode with 8-Bit DRAM
Clock H1
The first byte write transfer of the word burst starts in H1. During H1, the MCF5206e drives
the row address on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives
SIZ[1:0] to $2 indicating a word transfer, and asserts TS. The address driven on A[27:9]
corresponds to the row address for the first byte transfer of the burst.
Clock L1
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
Clock H2
The MCF5206e negates TS
, drives the column address on A[27:9], and begins driving the
data on D[31:24].
Clock L2
The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9].
CLK
A[27:9]
RAS
CAS[0]
DRAMW
D[31:24]
TS
INTERNAL TA
ROW COL COL
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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