Datasheet

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DRAM Controller
11-24 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-8. Longword Read Transfer Followed by a Page Hit Longword Read
Transfer in Fast Page Mode with 32-Bit DRAM
Clock H1
The longword read transfer starts in H1. During H1, the MCF5206e drives the row address
on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $0
indicating a longword transfer, and asserts TS.
Clock L1
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
Clock H2
The MCF5206e negates TS
, and drives the column address on A[27:9].
Clock L2
The MCF5206e asserts CAS
[3:0] to indicate the column address is valid on A[27:9]. At
this point the DRAM turns on its output drivers and drives data on D[31:0].
CLK
A[27:9]
RAS
CAS[3:0]
DRAMW
D[31:0]
TS
INTERNAL TA
ROW
COL
COL
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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