Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-25
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Clock H3
The internal transfer acknowledge asserts to indicate that the longword read transfer will
be completed and that data on D[31:0] will be registered on the next rising edge of CLK.
Clock H4
The MCF5206e negates the internal transfer acknowledge and CAS[3:0], ending the
longword read transfer. At this point the new page has been opened; therefore, the
MCF5206e continues to assert RAS. Once CAS[3:0] are negated the DRAM three-states
D[31:0]. The negation of CAS[3:0] begins the CAS precharge.
Clock H6
Clock H6 is the earliest the next transfer initiated by the ColdFire core can start. In this
case, a page-hit longword read is shown. The page-hit longword read transfer starts in H6.
During H6, the MCF5206e drives the column address on A[27:9], drives DRAMW high
indicating a DRAM read transfer, drives SIZ[1:0] to $0 indicating a longword transfer, and
asserts TS.
Clock L6
The MCF5206e asserts CAS[3:0] to indicate the column address is valid on A[27:9]. At
this point, the DRAM drives data on D[31:0].
Clock H7
The internal transfer acknowledge asserts to indicate that the longword read transfer will
be completed and that data on D[31:0] will be registered on the next rising edge of CLK.
Clock H8
The MCF5206e negates the internal transfer acknowledge and CAS[3:0], ending the
page-hit longword read transfer. Since the DRAM bank is in Fast Page Mode, the
MCF5206e continues to assert RAS
. Once CAS[3:0] are negated the DRAM three-states
D[31:0]. The negation of CAS
[3:0] begins the CAS precharge.
11.3.4.3 PAGE-HIT WRITE TRANSFER IN FAST PAGE MODE. A write transfer to an
open page results in a page-hit write. The timing of page-hit write transfers differs from the
timing of page-hit read transfers. On a page-hit write transfer, CAS is asserted one cycle
later than in a page-hit read transfer. This difference is due to the write data not being
driven until the cycle after TS
is asserted while data must be set up prior to CAS assertion.
The start of a page-hit write transfer to a DRAM bank in fast page mode can be delayed
by the DRAMC until the programmed CAS
precharge time is reached.
The fastest possible nonburst page-hit write transfer in fast page mode requires 3 clocks.
The fastest possible burst page-hit write transfer in fast page mode requires 3 clocks for
the initial transfer and 2 clocks for all secondary writes. You can program the DCTR to
generate slower fast page mode transfers.
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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