Datasheet

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DRAM Controller
11-26 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-9 shows the timing of a page being opened by a word write transfer to a 16-bit
port in Fast Page Mode. The first word write transfer is followed by a page-hit word write
transfer. The timing of the page-hit write transfer is the same regardless of whether the
page was opened by a burst read, burst write, nonburst read, or nonburst write transfer.
Figure 11-9. Word Write Transfer Followed by a Page-Hit Word Write Transfer in
Fast Page Mode with 16-bit DRAM
Clock H1
The first word write transfer starts in H1. During H1, the MCF5206e drives the row address
on A[27:9], drives DRAMW low indicating a DRAM write transfer, drives SIZ[1:0] to $2
indicating a word transfer, and asserts TS.
Clock L1
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
Clock H2
The MCF5206e negates TS
, drives the column address on A[27:9], and begins driving the
data on D[31:16].
CLK
A
RAS
CAS[1:0]
DRAMW
D[31:16]
TS
INTERNAL TA
ROW
COL
COL
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8
H9
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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