Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-27
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Clock L2
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9].
Clock H3
The internal transfer acknowledge asserts to indicate that the word write transfer will be
completed on the next rising edge of CLK.
Clock H4
The MCF5206e negates the internal transfer acknowledge and CAS[1:0], ending the first
word write transfer. At this point, the new page has been opened; therefore, the
MCF5206e continues to assert RAS. The negation of CAS[1:0] begins the CAS
precharge. When the write is completed, the MCF5206e three-states D[31:0].
Clock H6
Clock H6 is the earliest the next transfer initiated by the ColdFire core can start. In this
case, a page-hit word write transfer is shown. The word write transfer starts in H6. During
H6, the MCF5206e drives the column address on A[27:9], drives DRAMW low indicating
a DRAM write transfer, drives SIZ[1:0] to $2 indicating a word transfer, and asserts TS.
Clock H7
The MCF5206e negates TS, drives the column address on A[27:9], and begins driving the
data on D[31:16].
Clock L7
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9].
Clock H8
The internal transfer acknowledge asserts to indicate that the word write transfer will be
completed on the next rising edge of CLK.
Clock H9
The MCF5206e negates the internal transfer acknowledge and CAS[1:0], ending the
second word write transfer. Because the DRAM bank is in fast page mode, the MCF5206e
continues to assert RAS
. The negation of CAS[1:0] begins the CAS precharge. When the
write is completed, the MCF5206e three-states D[31:0].
11.3.4.4 PAGE MISS TRANSFER IN FAST PAGE MODE.
There is a potential performance penalty when using fast page mode. If a DRAM transfer
misses the open page, the start of the transfer will be delayed while RAS
precharges.
Therefore, fast page mode can increase performance when many successive transfers hit
Fr
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Freescale Semiconductor, Inc.
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