Datasheet

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DRAM Controller
11-28 MCF5206e USER’S MANUAL MOTOROLA
in the same page, but can also decrease performance when successive transfers hit in
different pages.
In cases where a page is open in one bank and a transfer hits in the other bank, the
transfer is not delayed because the second bank has already been precharged.
The fastest possible page miss transfer in fast page mode requires 4 clocks. The total
number of clocks in a page miss transfer is the RAS precharge time, which causes the
start of the transfer to be delayed (1 cycle for the fastest page miss transfer), plus the
length of a fast page mode transfer to a new page (3 cycles for the fastest page miss
transfer).
Figure 11-10 shows the timing of a page miss transfer in fast page mode. In this example,
a page is opened by a byte read transfer to an 8-bit port. Then a second byte read transfer
starts internally which misses the open page. Therefore, RAS must be precharged and a
new page must be opened. The timing of the page-miss write transfer is the same as the
timing of a page-miss read transfer.
Figure 11-10. Byte Read Transfer Followed by a Page-Miss Byte Read Transfer in
Fast Page Mode with 8-Bit DRAM
CLK
A
RAS
CAS[0]
DRAMW
D[31:24]
TS
Internal TA
ROW COL
COL
ROW
H9 L9 H10 L10 H11
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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