Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-29
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Clock H1
The first DRAM read transfer starts in H1. During H1, the MCF5206e drives the row
address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives SIZ[1:0]
to $1 indicating a byte transfer, and asserts TS.
Clock L1
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
Clock H2
The MCF5206e negates TS, and drives the column address on A[27:9].
Clock L2
The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9]. At this
point the DRAM drives data on D[31:24].
Clock H3
The internal transfer acknowledge asserts to indicate that the byte read transfer will be
completed and data on D[31:24] will be registered on the next rising edge of CLK.
Clock H4
The MCF5206e negates the internal transfer acknowledge and CAS[0], ending the first
byte read transfer. At this point, the new page has been opened; therefore, the MCF5206e
continues to assert RAS. Once CAS[0] is negated, the DRAM disables its output drivers
and D[31:0] is three-stated. The negation of CAS[0] begins the CAS precharge.
Clock H5/L5
A byte read transfer to the same DRAM bank is generated internally by the ColdFire core.
This transfer misses the open page.
Clock H6
The ColdFire core initiated a DRAM transfer on the previous cycle that misses the open
page. Therefore, the MCF5206e negates RAS, beginning the RAS precharge. Once the
RAS precharge time has been reached, a transfer to a new page can start.
Clock H7
The byte read transfer to a new page starts in H7. During H7, the MCF5206e drives the
row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives
SIZ[1:0] to $1 indicating a byte transfer, and asserts TS.
Clock L7
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...