Datasheet

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DRAM Controller
11-30 MCF5206e USER’S MANUAL MOTOROLA
The RAS precharge time has been met, so the MCF5206e asserts RAS is to indicate the
row address is valid on A[27:9].
Clock H8
The MCF5206e negates TS, and drives the column address on A[27:9].
Clock L8
The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9]. At this
point the DRAM drives data on D[31:24].
Clock H9
The internal transfer acknowledge asserts to indicate that the byte read transfer will be
completed and data on D[31:24] will be registered on the next rising edge of CLK.
Clock H10
The MCF5206e negates the internal transfer acknowledge and CAS[0], ending the first
byte read transfer. At this point, the new page has been opened; therefore, the MCF5206e
continues to assert RAS. Once CAS[0] is negated, the DRAM disables its output drivers
and D[31:0] is three-stated. The negation of CAS[0] begins the CAS precharge.
11.3.4.5 BUS ARBITRATION. If the MCF5206e loses bus mastership while a page is
open (RAS is asserted), RAS is precharged. The RAS precharge timing depends on
whether an active fast page mode DRAM transfer is in progress, whether a non-DRAM
transfer is in progress, or whether the external bus is idle.
If the BL bit in the SIMR is cleared and BG is negated while an active fast page mode
DRAM transfer is in progress, BD remains asserted until the transfer is complete. Once
the DRAM transfer completes, the MCF5206e negates BD and begin precharging RAS.
In the case where the BL bit in the SIMR is cleared and BG
is negated while a nonDRAM
transfer is in progress and a page is open, the MCF5206e begins precharging RAS
on the
cycle following the negation of BG, even though BD remains asserted until the completion
of the nonDRAM transfer.
If the BL bit in the SIMR is cleared and BG is negated while the external bus is idle and a
page is open, the MCF5206e negates BD and begins precharging RAS on the cycle
following the negation of BG
.
When the BL bit in the SIMR is set to 1 and BG
is asserted, the bus is locked with the
MCF5206e. If BG is negated while the bus is locked and a page is open, RAS and BD
remains asserted, because the MCF5206e maintains bus mastership regardless of BG
when the bus is locked.
Fr
eescale S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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