Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-31
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NOTE
Fast page mode is not supported for external master DRAM
transfers. A DRAM bank programmed for fast page mode,
operates in fast page mode for ColdFire core initiated
transfers, but operates in burst page mode for external master
initiated transfers.
Figure 11-11 shows the effect of bus arbitration on the DRAM signals when the external
bus is idle and a page is open in fast page mode.
Figure 11-11. Bus Arbitration in Fast Page Mode
Clock H1
A Fast Page Mode transfer starts in H1. During H1, the MCF5206e drives the row address
on A[27:9], and asserts TS
.
Clock L1
The MCF5206e asserts RAS
to indicate the row address is valid on A[27:9].
Clock H2
The MCF5206e negates TS, and drives the column address on A[27:9].
Clock L2
CLK
A[27:9]
RAS
CAS
TS
INTERNAL TA
BG
BD
ROW COL
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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