Datasheet

LIST OF TABLES (Continued)
Figure Page
Number Title Number
MOTOROLA MCF5206e USER’S MANUAL xxix
9-1. Data Bus Byte Write-Enable Signals.............................................................. 9-2
9-2. Maximum Memory Bank Sizes........................................................................ 9-4
9-3. Chip-Select, DRAM and Default Memory Address Decoding Priority............. 9-6
9-4. Memory Map of Chip-Select Registers ........................................................ 9-27
9-5. BA Field Comparisons for Alternate Master Transfers................................. 9-29
9-6. IRQ4 and IRQ1 Selection of CS[0] Port Size................................................ 9-32
9-7. IRQ7 Selection of CS[0] Acknowledge Generation....................................... 9-32
9-8. Port Size Encodings...................................................................................... 9-39
10-1. Memory Map of Parallel Port Registers ........................................................ 10-1
10-2. Data Direction Register Bit Assignments ...................................................... 10-2
10-3. Data Register Bit Assignments ..................................................................... 10-3
11-1. CAS Assertion.............................................................................................. 11-2
11-2. Maximum DRAM Bank Sizes........................................................................ 11-3
11-3. DRAM Bank Programming Example 1.......................................................... 11-6
11-4. Chip-Select, DRAM and Default Memory Address Decoding Priority........... 11-7
11-5. DRAM Bank Programming Example 2.......................................................... 11-8
11-6. 8-bit Port Size Address Multiplexing Configurations ................................... 11-11
11-7. 16-bit Port Size Address Multiplexing Configurations ................................ 11-12
11-8. 32-bit Port Size Address Multiplexing Configurations ................................ 11-13
11-9. Bank Page Size Versus Actual DRAM Page Size ...................................... 11-14
11-10. Memory Map of DRAM Controller Registers............................................... 11-51
12-1. UART Module Programming Model ............................................................ 12-17
12-2. PMx and PT Control Bits............................................................................. 12-18
12-3. B/Cx Control Bits......................................................................................... 12-19
12-4. CMx Control Bits ......................................................................................... 12-19
12-5. SBx Control Bits......................................................................................... 12-20
12-6. RCSx Control Bits ....................................................................................... 12-24
12-7. TCSx Control Bits........................................................................................ 12-24
12-8. MISCx Control Bits...................................................................................... 12-25
12-9. TCx Control Bits.......................................................................................... 12-26
12-10. RCx Control Bits.......................................................................................... 12-27
13-1. M-Bus Interface Programmer’s Model .......................................................... 13-6
13-2. MBUS Prescalar Values............................................................................... 13-7
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eescale S
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or
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