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DRAM Controller
11-32 MCF5206e USER’S MANUAL MOTOROLA
The MCF5206e asserts CAS to indicate the column address is valid on A[27:9].
Clock H3
The internal transfer acknowledge asserts to indicate that the current transfer will be
completed on the next rising edge of CLK.
Clock H4
The MCF5206e negates the internal transfer acknowledge and CAS, ending the transfer.
At this point, a page has been opened; therefore, the MCF5206e continues to assert RAS.
The negation of CAS begins the CAS precharge.
Clock H6
After the bus has idled for two clocks, BG is negated (while the BL bit in the SIMR is
cleared).
Clock H7
The MCF5206e then three-states the external bus signals, negates RAS (closing the
page), and negates BD, relinquishing mastership of the bus. The negation of RAS begins
the RAS precharge.
11.3.5 Burst Page-Mode Operation
Burst page mode performs fast page mode transfers only for burst transfers. A burst
transfer to DRAM occurs any time the operand size is larger than the DRAM bank port
size (e.g., line transfer to a 32-bit port, longword transfer to an 8-bit port). After completing
the burst, the MCF5206e negates RAS, closing the page. Because all secondary transfers
of a burst are guaranteed to be page hits, a page miss never occurs in burst page mode.
Nonburst transfers occur as in normal mode. Therefore, burst page mode always provides
the same or better performance than normal mode.
The timing of read and write transfers is identical in burst page mode, with the exception
of when the DRAM drives data on reads and when the MCF5206e drives data on writes.
The fastest possible burst transfer in burst page mode requires three clocks for the first
transfer and two clocks on the secondary transfers. The fastest possible nonburst transfer
in burst page mode requires three clocks. You can program the DCTR to generate slower
burst page mode transfers.
Figure 11-12 shows a longword write transfer followed by a word read transfer to a 16-bit
port with burst page mode enabled for the bank. The burst longword write transfer is
handled as in fast page mode with the initial word transfer of the burst taking three cycles
and the secondary word transfer taking two cycles. However, in burst page mode, the
MCF5206e precharges RAS
once the burst transfer is complete. The second transfer (a
word read) is executed as in normal mode as it is not a burst transfer.
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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