Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-33
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Figure 11-12. Longword Write Transfer Followed by a Word Read Transfer in Burst
Page Mode with 16-Bit DRAM
Clock H1
The first word write transfer of the longword burst starts in H1. During H1, the MCF5206e
drives the row address on A[27:9], drives DRAMW low indicating a DRAM write transfer,
drives SIZ[1:0] to $0 indicating a longword transfer, and asserts TS.
Clock L1
The MCF5206e asserts RAS
to indicate the row address is valid on A[27:9].
Clock H2
The MCF5206e negates TS
, drives the column address on A[27:9], and begins driving the
data on D[31:16].
Clock L2
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9].
CLK
A[27:9]
RAS
CAS[1:0]
DRAMW
D[31:16]
TS
INTERNAL TA
ROW COL COL COLROW
H9 L9 H10 L10 H11
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...