Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-35
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Clock L9
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9]. At
this point the DRAM drives the data on D[31:16].
Clock H10
The internal transfer acknowledge asserts to indicate that the current transfer will be
completed and the data on D[31:16] will be registered on the next rising edge of CLK.
Clock H11
The MCF5206e registers the read data driven by the DRAM, and negates the internal
transfer acknowledge, RAS and CAS[1:0], ending the word read transfer. This begins the
RAS precharge. Once CAS is negated, the DRAM disables its output drivers and D[31:0]
is three-stated.
11.3.6 Extended Data-Out (EDO) DRAM Operation
Extended data-out (EDO) DRAMs do not three-state their output drivers at the negation
of CAS on page read transfers as do fast-page-mode DRAMs. Instead, data remains valid
until some time (typically 5 ns) after the next falling edge of CAS. This allows CAS to be
precharged without the output data going invalid. The result is that a system using slower,
less expensive EDO DRAM can achieve the same performance as a system using faster,
more expensive fast-page-mode DRAMs.
The MCF5206e supports EDO DRAM with a CAS timing that takes advantage of the read
data remaining valid after CAS negates. To enable the EDO CAS timing for both DRAM
banks, set the EDO Enable bit in the DCTR to 1. When set to 1, CAS negates one-half
clock cycle earlier for fast-page-mode and burst-page-mode transfers than when the EDO
Enable bit is cleared. At higher clock frequencies, the EDO CAS timing allows slower, less
expensive EDO DRAMs to be used, since the CAS precharge starts before data is
registered on read transfers. For the fastest timing in fast page mode or burst page mode,
having the EDO Enable bit set gives one clock of CAS
precharge time, rather than one-
half of a clock with the EDO Enable bit cleared.
Since EDO DRAM continues to drive data after a read as long as RAS
is asserted, be
careful with the system design using EDO DRAM to ensure bus contention does not occur
when a nonDRAM transfer occurs while a page is open in fast page mode.
NOTE
Failure to use normal mode or burst page mode with EDO
DRAM without external circuitry to control the DRAM output
drivers could result in damage to the MCF5206e and the
system.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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