Datasheet

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DRAM Controller
11-36 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-13 shows the timing of a word read in Fast Page Mode followed by a page miss
word read using 8-bit wide EDO DRAM (the EDO bit in the DCTR is set).
Figure 11-13. Word Read Transfer Followed by a Page Miss Byte Read Transfer in
Fast Page Mode with 8-Bit EDO DRAM
Clock H1
The first byte read transfer of the burst word transfer starts in H1. During H1, the
MCF5206e drives the row address on A[27:9], drives DRAMW high indicating a DRAM
write transfer, drives SIZ[1:0] to $2 indicating a byte transfer, and asserts TS
.
Clock L1
The MCF5206e asserts RAS
to indicate the row address is valid on A[27:9].
Clock H2
The MCF5206e negates TS, drives the column address on A[27:9].
Clock L2
The MCF5206e asserts CAS
[0] to indicate the column address is valid on A[27:9]. At this
point the EDO DRAM drives data on D[31:24].
CLK
A[27:9]
RAS
CAS[0]
DRAMW
D[31:24]
TS
INTERNAL TA
ROW COL
COL ROW COL
H9 L9 H10 L10 H11
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8
L11
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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