Datasheet

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DRAM Controller
11-38 MCF5206e USER’S MANUAL MOTOROLA
Clock H8
The ColdFire core initiated a DRAM transfer on the previous cycle that missed the open
page. Therefore, the MCF5206e negates RAS, beginning the RAS precharge. Once the
RAS precharge time has been reached, a transfer to a new page can start. Once RAS is
negated, the EDO DRAM disables its output drivers and D[31:0] is three-stated.
Clock H9
The byte read transfer to a new page starts in H9. During H9, the MCF5206e drives the
row address on A[27:9], drives DRAMW high indicating a DRAM read transfer, drives
SIZ[1:0] to $1 indicating a byte transfer, and asserts TS.
Clock L9
Now that the RAS precharge time has been reached, the MCF5206e asserts RAS is to
indicate the row address is valid on A[27:9].
Clock H10
The MCF5206e negates TS, drives the column address on A[27:9].
Clock L10
The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9]. At this
point the EDO DRAM drives data on D[31:24].
Clock H11
The internal transfer acknowledge asserts to indicate that the first byte read transfer of the
word burst will be completed and the data on D[31:24] will be registered on the next rising
edge of CLK.
Clock H12
The MCF5206e negates the internal transfer acknowledge, ending the byte-read transfer.
Because the bank is in fast page mode, MCF5206e continues to assert RAS. Because
RAS remains asserted, the EDO DRAM continues to drive the data from the previous read
transfer on D[31:24].
11.3.7 Refresh Operation
The DRAMC supports CAS-before-RAS refresh. Refresh cycles can be generated while
nonDRAM transfers are actively using the external bus. Only transfers accessing the
DRAM banks delays a refresh cycle. Both DRAM banks are refreshed on each refresh
cycle.
The value stored in the RC field of the DCRR determines the rate at which the refresh
controller internally requests refreshes in the DRAMC. The DRAMC does not immediately
Fr
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Freescale Semiconductor, Inc.
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