Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-39
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initiate a refresh cycle if a DRAM transfer is occurring when the internal refresh request is
made. The DRAMC waits until the active DRAM transfer is complete and then initiates the
DRAM refresh cycle. Refresh cycles occur immediately after the internal refresh request
is made during idle bus cycles and during nonDRAM transfers.
NOTE
Add margin when determining the value to program into the
RC field of the DCRR so that a refresh cycle delayed by the
longest possible DRAM transfer does not violate the refresh
rate specified for the DRAMs being used.
Programming the RC field in the DCRR to $000 causes internal refresh requests to occur
at the slowest rate—once every 65,536 system clock cycles. Programming the RC field in
the DCRR to $001 causes internal refresh requests to occur at the fastest rate—once
every 16 system clocks. If multiple refresh requests occur while waiting for a DRAM
transfer to finish, only one refresh cycle is generated.
Writing to the DCRR causes an internal refresh request to occur and the refresh counter
to be reloaded. If the DCRR is written while a refresh request is pending, only one refresh
cycle is generated. If the DCRR is written while a refresh cycle is in progress, another
refresh cycle is not generated after the one in progress completes.
The refresh period is the amount of time between internal refresh requests. The refresh
period can be calculated from the value programmed in the RC field of the DCRR using
the following equations:
For RC>$000:
Refresh period = RC x16 x (1/system clock frequency)
For RC=$000:
Refresh period = 65536 x (1/system clock frequency)
When the DRAMC initiates a refresh cycle, it delays any DRAM transfer initiated by the
ColdFire core or by an external master until the RAS precharge is complete at the end of
refresh cycle. If a DRAM transfer is initiated by the ColdFire core while a refresh cycle is
in progress and the MCF5206e is not the bus master, bus request (BR
) is not asserted
until after the refresh completes.
A master reset terminates any active refresh cycle and resets the refresh controller.
Master reset is required on all power-on resets. During a master reset, refresh cycles do
not occur; after a master reset, refreshes occur at the slowest rate (DCRR is initialized to
$0000).
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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