Datasheet

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DRAM Controller
11-40 MCF5206e USER’S MANUAL MOTOROLA
NOTE
During a master reset, the DCCR is reset to $000 (giving the
slowest refresh rate) and the DCTR is reset to $0000 (giving
the fastest waveform timing). After a master reset, the
initialization sequence should program the DRAMC Refresh
Register (DCRR) and the DRAMC Timing Register (DCTR)
such that refresh cycles are generated at the required rate and
with the required timing for the DRAM in the system. In
general, DRAMs require an initial pause after power-up and
require a minimum number of DRAM cycles to be run before
the DRAM is ready for use. This initialization sequence must
be handled through software.
Normal reset does not affect a refresh cycle in progress and does not reset the refresh
controller. Refreshes occur during a normal reset with the timing specified in the DCTR
and at the rate specified in the DCRR.
11.3.8 External Master Use of the DRAM Controller
The DRAMC can support external master-initiated transfers. When an external master is
the bus master, the MCF5206e registers all available address signals, R/W, and SIZ[1:0]
on the rising edge of clock when TS is asserted. Based on the address, direction, and data
size, the DRAMC asserts RAS, CAS, DRAMW, and conditionally drives the address bus.
NOTE
If you do not want the MCF5206e DRAMC to respond on
external master transfers, TS should not be asserted to the
MCF5206e during external master transfers. However, the
MCF5206e continues to generate DRAM refresh cycles while
the bus is granted to an external master.
NOTE
The driving of the data on writes and the latching of data on
reads based on the data size and port size of the DRAM is the
responsibility of the external master. The MCF5206e does not
drive the data bus when it is not master of the external bus.
The MCF5206e can delay the access to DRAM for an external master initiated transfer if
a refresh request is pending or if the programmed RAS precharge time has not been
reached. If there is a refresh cycle in progress or if there is a refresh request pending when
an external master starts a DRAM transfer, the MCF5206e does not start driving the row
address and assert RAS until the RAS precharge time has been reached after completing
the refresh cycle. If a refresh request occurs during an external master DRAM transfer,
the refresh cycle is delayed until the external master DRAM transfer is completed. If the
programmed RAS precharge time from the previous DRAM transfer has not been
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