Datasheet

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DRAM Controller
11-42 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-14 illustrates the timing of an external master DRAM byte read transfer followed
by a byte write transfer to a 8-bit port in normal mode.
Figure 11-14. External Master Byte Read Transfer Followed by Byte Write Transfer
in Normal Mode with 16-Bit DRAM
Clock H1/L1
An external master is the current bus master. The external master starts a DRAM transfer
by driving A[27:0], driving R/W high indicating a read transfer, driving SIZ[1:0] to $1
indicating a byte transfer, and asserting TS
. These inputs to the MCF5206e must be set
up with respect to the rising edge of CLK H2.
Clock H2
On the rising edge of CLK when TS
is asserted, the MCF5206e registers the address and
attribute signals. The MCF5206e internally decodes these signals and determine if the
external master transfer is a DRAM access. The external master negates TS and must
three-state A[27:0] after the rising edge of CLK H2, if the internal address multiplexing is
to be used.
CLK
A[27:0]
RAS
CAS[0]
DRAMW
D[31:24]
TS
TA
COLA COLAROWAROWA
H9 L9 H10 L10 H11
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8
L11
R/W
SIZ[1:0]
$1
$1
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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