Datasheet

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
DRAM Controller
11-44 MCF5206e USER’S MANUAL MOTOROLA
Clock H8
The MCF5206e has determined that the external master transfer is a DRAM access, so
the MCF5206e drives the A[27:0] with the same value as was registered on the rising
edge of H2. A[27:9] contains the row address for the DRAM. The MCF5206e also drives
DRAMW
low, indicating a DRAM write cycle.
Clock L8
The MCF5206e asserts RAS
to indicate the row address is valid on A[27:9].
Clock H9
The MCF5206e internally multiplexes the address and drives out the column address on
A[27:9]. The MCF5206e also actively drives TA negated.
Clock L9
The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9]. The
external master must set up and hold the data with respect to the falling edge of CAS[0]
based on the DRAM specifications.
Clock H10
The MCF5206e asserts the TA signal to indicate that the byte write transfer will be
completed on the next rising edge of CLK.
Clock H11
The MCF5206e then negates RAS, CAS[0], and TA, and three-state the address bus,
ending the byte write transfer. The negation of RAS starts the RAS precharge. Once
A[27:0] has three-stated, the external master can start another transfer.
Clock H12
The MCF5206e three-states TA
.
11.3.8.2 EXTERNAL MASTER BURST TRANSFER IN NORMAL MODE. A burst
transfer to DRAM is generated when the operand size is larger than the DRAM bank port
size (e.g., line transfer to a 32-bit port, longword transfer to an 8-bit port). On DRAM burst
transfers, the external master should assert TS
only once. The start of the secondary
transfers of a burst is delayed by the DRAMC until the programmed RAS precharge time
is met.
The timing of external master burst reads and burst writes is identical in normal page
mode, with the exception of when the DRAM drives data on reads and when the external
master drives data on writes.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...