Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-45
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The fastest possible external master burst transfer in normal mode requires 5 clocks for
the first transfer of the burst and 4 clocks for the secondary transfers (including a 1.5 clock
RAS precharge time). You can program the DCTR to generate slower normal mode
transfers.
Figure 11-15 illustrates the timing of a external master longword write transfer to a 16-bit
DRAM in normal mode. The timing of the first transfer of the burst operates the same as
the nonburst case. After the first transfer of the burst completes, TA is negated and the
row address is driven again by the MCF5206e. The MCF5206e asserts RAS after the RAS
precharge time is met and the transfer completes the same as in the nonburst case.
Driving the write data in the correct byte lanes at the proper time to meet the specifications
of the DRAM is the responsibility of the external master.
Figure 11-15. External Master Longword Write Transfer in Normal Mode with 16-Bit
DRAM
Clock H1/L1
An external master is the current bus master. The external master starts a DRAM transfer
by driving A[27:0], driving R/W
low indicating a write transfer, driving SIZ[1:0] to $0
indicating a longword transfer, and asserting TS
. These inputs to the MCF5206e must be
set up with respect to the rising edge of CLK H2. The external master must drive the data
CLK
A[27:0]
RAS
CAS[1:0]
DRAMW
D[31:16]
TS
TA
COL COLROWROW
H9 L9 H10 L10 H11
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8
R/W
SIZ[1:0]
$0
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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