Datasheet

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DRAM Controller
11-46 MCF5206e USER’S MANUAL MOTOROLA
in the correct byte lanes based on the data size and the port size of the DRAM, and must
drive the data to meet the timing specifications of the DRAM. In this case, the external
master should drive the write data on D[31:16].
Clock H2
On the rising edge of CLK when TS is asserted, the MCF5206e registers the address and
attribute signals. It internally decodes these signals and determines if the external master
transfer is a DRAM access. The external master negates TS and must three-state A[27:0]
after the rising edge of CLK H2, if the internal address multiplexing is to be used.
Clock H3
The MCF5206e has determined that the external master transfer is a DRAM access, so
the MCF5206e drives A[27:0] with the same value as was registered on the rising edge of
H2. A[27:9] contain the DRAM row address. The MCF5206e also drives DRAMW low
indicating a DRAM write cycle.
Clock L3
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
Clock H4
The MCF5206e internally multiplexes the address and drives out the column address on
A[27:9]. The MCF5206e also actively drives TA negated.
Clock L4
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9]. The
external master must set up and hold the first word of data on D[31:16] with respect to the
falling edge of CAS[1:0] based on the DRAM specifications.
Clock H5
The MCF5206e asserts the TA signal to indicate that the first word write transfer of the
longword burst will be completed on the next rising edge of CLK.
Clock H6
The MCF5206e negates RAS, CAS[1:0], and TA, ending the first word transfer of the
longword burst. The negation of RAS starts the RAS precharge. The MCF5206e drives
the row address again for second word transfer of the longword burst write.
Clock L7
Once the RAS precharge time has been met, the MCF5206e asserts RAS to indicate the
row address is valid on A[27:9].
Fr
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Freescale Semiconductor, Inc.
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