Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-47
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Clock H8
The MCF5206e internally increments and multiplexes the address and drives out the
column address on A[27:9] for the second word transfer of the longword burst write.
Clock L8
Clock L8 is the same as Clock L4. The MCF5206e asserts CAS[1:0] to indicate the column
address is valid on A[27:9]. The external master must set up and hold the second word of
data on D[31:16] with respect to the falling edge of CAS[1:0] based on the DRAM
specifications.
Clock H9
Clock H9 is the same as Clock H5. The MCF5206e asserts the TA signal to indicate that
the second word write transfer of the longword burst will be completed on the next rising
edge of CLK.
Clock H10
The MCF5206e negates RAS, CAS[1:0], and TA, and three-states A[27:0], ending the
second word transfer of the longword burst. The negation of RAS starts the RAS
precharge. Once A[27:0] has three-stated, the external master can start another transfer.
Clock H11
The MCF5206e three-states TA.
11.3.8.3 EXTERNAL MASTER BURST TRANSFER IN BURST PAGE MODE. Burst
page mode does fast page mode transfers only for burst transfers. A burst transfer to
DRAM is generated any time the operand size is larger than the DRAM bank port size
(e.g., line transfer to a 32-bit port, longword transfer to an 8-bit port). After completing the
burst transfer, the MCF5206e negates RAS, closing the page. Because all secondary
transfers of a burst are guaranteed to be page hits, a page miss never occurs in burst page
mode. Nonburst transfers occur as in normal mode (for nonburst transfers in burst page
mode, refer to Section 11.3.8.1 External Master Non Burst Transfer in Normal Mode).
Therefore, burst page mode always provides the same or better performance than normal
mode.
Because the DRAMC does not support fast page mode for external master transfers, a
DRAM bank programmed for either burst page mode or fast page mode operates as burst
page mode.
The timing of read transfers and write transfers is identical in burst page mode, with the
exception of when the DRAM drives data on reads and when the external master drives
data on writes.
The fastest possible external master burst transfer in burst page mode requires 5 clocks
for the first transfer of the burst and two clocks for the secondary transfers. The fastest
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