Datasheet

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DRAM Controller
11-48 MCF5206e USER’S MANUAL MOTOROLA
possible nonburst transfer in burst page mode requires 5 clocks. You can program the
DCTR to generate slower burst-page-mode transfers.
Figure 11-16 illustrates the timing of a word read transfer to an 8-bit DRAM in burst page
mode. In burst page mode after the first byte transfer of the burst is complete, RAS
remains asserted while CAS
[0] and TA are negated and the column address of the
second byte transfer of the burst is driven. After the CAS
precharge time is met, CAS[0]
asserts for the second byte read transfer. When the second byte read transfer is
completed, RAS, CAS[0], and TA are negated, ending the burst transfer.
Figure 11-16. External Master Word Read Transfer in Burst Page Mode with 8-Bit
DRAM
Clock H1/L1
An external master is the current bus master. The external master starts a DRAM burst
word-write transfer by driving A[27:0], driving R/W high indicating a read transfer, driving
CLK
A[27:0]
RAS
CAS
DRAMW
D[31:24]
TS
TA
COL COLROW
H9
H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7 H8 L8
R/W
SIZ[1:0]
$2
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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