Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-49
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SIZ[1:0] to $2 indicating a word transfer, and asserting TS. These inputs to the MCF5206e
must be set up with respect to the rising edge of CLK H2.
Clock H2
On the rising edge of CLK when TS is asserted, the MCF5206e registers the address and
attribute signals. It internally decodes these signals and determines if the external master
transfer is a DRAM access. The external master negates TS and must three-state A[27:0]
after the rising edge of CLK H2, if the internal address multiplexing is to be used.
Clock H3
The MCF5206e has determined that the external master transfer is a DRAM access, so
the MCF5206e drives A[27:0] with the same value as was registered on the rising edge of
H2. A[27:9] contain the DRAM row address. The MCF5206e also drives DRAMW high
indicating a DRAM read cycle.
Clock L3
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
Clock H4
The MCF5206e internally multiplexes the address and drives out the column address on
A[27:9]. The MCF5206e also actively drives TA negated.
Clock L4
The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9]. At this
point the DRAM drives the data on D[31:24].
Clock H5
The MCF5206e asserts the TA signal to indicate that the first byte read transfer of the
burst will be completed and the read data will be valid on D[31:24] on the next rising edge
of CLK.
Clock H6
The MCF5206e negates CAS[0], and TA, ending the first byte read transfer of the burst.
Because the bank is in burst page mode, the MCF5206e continues to assert RAS
. The
negation of CAS
[0] starts the CAS precharge. The MCF5206e drives the column address
on A[27:9] for second byte read transfer of the burst.
Clock L6
After the CAS precharge time is met, the MCF5206e asserts CAS[0] to indicate the
column address is valid on A[27:9]. At this point the DRAM drives the data bus.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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