Datasheet

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DRAM Controller
11-50 MCF5206e USER’S MANUAL MOTOROLA
Clock H7
The MCF5206e asserts the TA signal to indicate that the first byte read transfer of the
burst will be completed and the read data will be valid on D[31:24] on the next rising edge
of CLK.
Clock H8
The MCF5206e negates RAS, CAS[0], and TA, and three-states A[27:0], ending the final
byte read transfer of the burst. Because the bank is in burst page mode, MCF5206e
negates RAS when the burst transfer is completed. The negation of RAS starts the RAS
precharge. Once A[27:0] has three-stated, the external master can start another transfer.
Clock H9
The MCF5206e three-states TA.
11.3.8.4 LIMITATIONS. Because the external and internal address buses differ in size
and address multiplexing occurs for transfers to DRAM, certain limitations exist for
external master use of the DRAMC.
• Fast page mode is not available for external master transfers. If a bank has this
featured enabled, then burst page mode is used for external master transfers and fast
page mode is used for ColdFire core-initiated transfers.
• The UC, UD, SC, and SD mask bits are ignored during external master-initiated
transfers. Therefore, if UC, UD, SC, and SD are all masked, that bank is available for
external master transfers even though the bank is unavailable for ColdFire core-
initiated transfers.
• In determining whether an external master transfer address hits in a DRAM bank, the
bits of the internal address bus which are unavailable externally are regarded as $0.
A[31:28] are always be set to $0 and A[27:24] are conditionally (based on PAR) be
set to $0. In order for a bank to be accessible for external-master transfers, the
address bits that are unavailable to the external master must either be set to 0 in the
DCAR or be masked in the DCMR.
• DRAM bank size is limited by the availability of A[27:24] as determined by the PAR
control register.
11.4 PROGRAMMING MODEL
11.4.1 DRAM Controller Registers Memory Map
Table 11-10 shows the memory map of all the DRAMC registers. The internal registers in
the DRAM controller are memory-mapped registers offset from the MBAR address
pointer.
The following lists several key notes regarding the programming model table:
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