Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-51
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• Addresses not assigned to a register and undefined register bits are reserved for
future expansion. Write accesses to these reserved address spaces and reserved
register bits have no effect; read accesses return zeros.
• The reset value column indicates the register initial value at master reset and normal
reset. Certain registers are uninitialized upon reset—they may contain random values
after reset.
• The access column indicates if the corresponding register allows both read/write
functionality (R/W), read-only functionality (R), or write-only functionality (W). If a read
access to a write-only register is attempted, zeros are returned. If a write access to a
read-only register is attempted, the access is ignored and no write occurs.
11.4.2 DRAM Controller Registers
11.4.2.1 DRAM CONTROLLER REFRESH REGISTER (DCRR). The DRAM Controller
Refresh Register (DCRR) controls the number of system clocks between refresh cycles.
The DCRR is a 16-bit read/write control register. The DCRR is set to $0000 by master
reset (corresponding to the slowest refresh rate) and is unaffected by normal reset.
Table 11-10. Memory Map of DRAM Controller Registers
ADDRESS NAME WIDTH DESCRIPTION RESET VALUE ACCESS
MBAR + $46 DCRR 16 DRAM Controller Refresh Master Reset: $0000
Normal Reset: uninitialized
R/W
MBAR + $4A DCTR 16 DRAM Controller Timing Register Master Reset: $0000
Normal Reset: uninitialized
R/W
MBAR + $4C DCAR0 16 DRAM Controller Address Register - Bank 0 Master Reset: uninitialized
Normal Reset: uninitialized
R/W
MBAR + $50 DCMR0 32 DRAM Controller Mask Register - Bank 0 Master Reset: uninitialized
Normal Reset: uninitialized
R/W
MBAR + $57 DCCR0 8 DRAM Controller Control Register- Bank 0 Master Reset: $00
Normal Reset: $00
R/W
MBAR + $58 DCAR1 16 DRAM Controller Address Register - Bank 1 Master Reset: uninitialized
Normal Reset: uninitialized
R/W
MBAR + $5C DCMR1 32 DRAM Controller Mask Register - Bank 1 Master Reset: uninitialized
Normal Reset: uninitialized
R/W
MBAR + $63 DCCR1 8 DRAM Controller Control Register - Bank 1 Master Reset: $00
Normal Reset: $00
R/W
----RC11RC10RC9RC8RC7RC6RC5RC4RC3RC2RC1RC0
1514131211109876543210
0000000000000000
MASTER RESET:
DRAM Controller Refresh Counter(DCRR)
Address MBAR + $46
NORMAL RESET:
0000------------
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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