Datasheet

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DRAM Controller
11-52 MCF5206e USER’S MANUAL MOTOROLA
RC11 - RC0 - Refresh Count
This field controls the frequency of refresh requests. The value stored in this field is
multiplied by 16 system clocks to determine the refresh period. The refresh period can
range from 16 system clocks to 65,536 system clocks. An RC field value of all zeros
corresponds to 65,536 system clocks. Any write to the DCRR forces a refresh cycle to
occur. The refresh period can be calculated using the following equations:
For RC>$000:
Refresh period = RC x16 x (1/system clock frequency)
For RC=$000:
Refresh period = 65536 x (1/system clock frequency)
11.4.2.2 DRAM CONTROLLER TIMING REGISTER (DCTR). The DCTR controls the
waveform timing for all DRAM transfers. The fields in this register control the RAS and
CAS waveform timing for all types of DRAM transfers provided by the DRAMC. The DCTR
is a 16-bit read/write control register. The DCTR is set to $0000 by master reset and is
unaffected by normal reset.
DAEM - Drive Multiplexed Address During External Master DRAM transfers
This field controls the MCF5206e output driver enables for the external address bus
during external master transfers that hit in DRAM address space. If DAEM is set to 1, the
portion of A[27]/CS
[7]/WE[0], A[26]/CS[6]/WE[1], A[25]/CS[5]/WE[2], A[24]/CS[4]/WE[3]
that are configured as address signals are driven along with A[23:0] to provide row and
column address multiplexing for external masters. This field does not affect the address
multiplexing for DRAM transfers initiated by the ColdFire core.
0 = Do not drive the external address signals as outputs during external master
DRAM transfers
1 = Drive the external address signals as outputs to provide row and column address
multiplexing during external master DRAM transfers
EDO - Extended Data-Out Enable
This field controls page mode CAS
timing. If the DRAM banks are populated with
extended data-out DRAM, the EDO Enable bit can be set to take advantage of the CAS
timing allowed by EDO DRAMs. The EDO Enable bit, along with the CAS and CP bits,
DAEM EDO - RCD - RSH1 RSH0 - - RP1 RP0 - CAS - CP CSR
1514131211109876543210
0000000000000000
MASTER RESET:
DRAM Controller Timing Register(DCTR)
Address MBAR + $4A
NORMAL RESET:
--0-0--00--0-0--
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Freescale Semiconductor, Inc.
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