Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-53
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control the CAS assertion and negation time during fast page mode and burst page mode
transfers. Refer to Figure 11-21 for a timing diagram of EDO DRAM page mode transfers.
0 = DRAM banks are populated with standard DRAM, do not use EDO CAS timing
1 = DRAM banks are populated with EDO DRAM, use EDO CAS timing
NOTE
If neither fast page mode or burst page mode are enabled in
the DRAM Control Register (DCCR), the EDO Enable bit has
no effect on the DRAM waveform timing.
RCD - RAS-to-CAS Delay Time
This field controls the number of system clocks between the assertion of RAS and the
assertion of CAS for transfers in normal mode and for the initial transfer to a page in fast
page mode and burst page mode. Because the column address is always driven 0.5
system clocks prior to the assertion of CAS, RCD affects the driving of the column
address. RCD does not affect refresh cycles. Refer to Figure 11-17 for normal mode
timing. Refer to Figures 11-18 and 11-19 for fast page mode and burst page mode timing.
0 = RAS asserts 1.0 system clock before the assertion of CAS
1 = RAS asserts 2.0 system clocks before the assertion of CAS
Figure 11-17. Normal Mode DRAM Transfer Timing
CLK
TS
A
RAS
CAS
D
INTERNAL TA
DRAMW
RCD
RSH
RP
Fr
eescale S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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