Datasheet

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DRAM Controller
11-54 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-18. Fast Page Mode or Burst Page Mode DRAM Transfer Timing
Figure 11-19. Fast Page Mode or Burst Page Mode DRAM Transfer Timing
RSH1 - RSH0 - RAS Hold Time
This field controls the number of system clocks that RAS
remains asserted after the
assertion of CAS
. This field controls RAS active timing for transfers in normal mode and
for the initial transfer in fast page mode and burst page mode. Refer to Figure 11-17 for
CLK
TS
A
RAS
CAS
D
INTERNAL TA
DRAMW
RCD
RSH
CP
CP
CAS
CLK
TS
A
RAS
CAS
D
internal TA
DRAMW
RCD RSH
CP
CP
CAS
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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