Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-55
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normal mode timing. Refer to Figures 11-19 and 11-21 for fast-page-mode and burst-
page-mode timing.
For transfers in normal mode:
00 = RAS negates 1.5 system clocks after the assertion of CAS
01 = RAS negates 2.5 system clocks after the assertion of CAS
10 = RAS negates 3.5 system clocks after the assertion of CAS
11 = Reserved
For the initial transfer in fast page mode and burst page mode with EDO Enable = 0:
00 = RAS negates 1.5 system clocks after the assertion of CAS
01 = RAS negates 2.5 system clocks after the assertion of CAS
10 = RAS negates 3.5 system clocks after the assertion of CAS
11 = Reserved
For initial transfer in fast page mode and burst page mode with EDO Enable = 1:
00 = RAS negates 1.0 system clock after the assertion of CAS
01 = RAS negates 2.0 system clocks after the assertion of CAS
10 = RAS negates 3.0 system clocks after the assertion of CAS
11 = Reserved
RP1 - RP0 - RAS Precharge Time
This field controls the number of system clocks RAS precharges when the bus master
requires back-to-back DRAM transfers in normal mode. RP also controls the number
system clocks RAS precharges after a refresh cycle or when a page is closed in fast page
mode or burst page mode. Refer to Figure 11-22 for refresh cycle timing. Refer to Figure
11-17 for normal mode timing. Refer to Figure 11-20 for fast page-mode timing.
00 = RAS precharges for 1.5 system clocks
01 = RAS precharges for 2.5 system clocks
10 = RAS precharges for 3.5 system clocks
11 = Reserved
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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