Datasheet

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DRAM Controller
11-56 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-20. Fast Page Mode Page Hit and Page Miss DRAM Transfer Timing
CAS - Column Address Strobe Time
This field, together with the EDO field, controls the number of system clocks that CAS
asserts on transfers once a page is open in fast page mode and burst page mode. Refer
to Figure 11-18 for timing diagrams of fast-page-mode or burst-page- mode transfers to
standard DRAMs and Figure 11-21 for fast-page-mode or burst-page-mode transfers to
EDO DRAMs.
For EDO = 0:
0 = CAS is asserted for 1.5 system clocks
1 = CAS is asserted for 2.5 system clocks
For EDO = 1:
0 = CAS
is asserted for 1.0 system clock
1 = CAS
is asserted for 2.0 system clocks
CLK
TS
A
RAS
CAS
D
INTERNAL TA
DRAMW
CAS
RP
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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