Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-57
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Figure 11-21. Fast Page Mode or Burst Page Mode EDO DRAM Transfer Timing
CP - CAS Precharge Time
This field, together with the EDO field, controls the number of system clocks that CAS is
negated after a page mode transfer. This field controls CAS timing for fast page mode and
burst page mode. Refer to Figures 11-6 and 11-7 for timing diagrams illustrating CAS
precharge timing in fast page mode and burst page mode using standard and EDO
DRAMs.
For EDO Enable = 0:
0 = CAS is negated for 0.5 system clocks
1 = CAS is negated for 1.5 system clocks
For EDO Enable = 1:
0 = CAS is negated for 1.0 system clock
1 = CAS is negated for 2.0 system clocks
CSR - CAS Setup Time for CAS Before RAS Refresh
This field controls the number of system clocks between the assertion of CAS and the
assertion of RAS
during refresh cycles. This field does not affect normal mode, fast page
mode, or burst-page-mode transfer timing. Refer to Figure 11-22 for refresh cycle timing.
0 = CAS
asserts 1.0 system clock before the assertion of RAS
1 = CAS asserts 2.0 system clocks before the assertion of RAS
CLK
TS
A
RAS
CAS
D
INTERNAL TA
DRAMW
RCD RSH CP CAS CP
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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