Datasheet

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DRAM Controller
11-58 MCF5206e USER’S MANUAL MOTOROLA
Figure 11-22. CAS Before RAS Refresh Cycle Timing
NOTE
The DCTR should not be written while an external master
transfer is in progress. The DCTR should be programmed as
part of the initialization sequence and external master DRAM
transfers should not be attempted until it has been written.
Failure to do so results in unpredictable operation.
11.4.2.3 DRAM CONTROLLER ADDRESS REGISTERS (DCAR0 - DCAR1). Each
DCAR holds the base address of the corresponding DRAM bank. Each DCAR is a 16-bit
read/write control register. All bits in DCAR0 - DCAR1 are unaffected by either master
reset or normal reset.
BA31-BA17 - Base Address
This field defines the base address location of each DRAM bank. These bits are
compared to bits 31-17 of the transfer address to determine if the DRAM bank is being
accessed.
NOTE
In determining whether an external master transfer address
hits in a DRAM bank, the portion of the address bus that is
unavailable externally is regarded as $0. That is, the external
master transfer address always has A[31:28] as $0 and those
bits of A[27:24] that are not programmed to be external
CLK
RAS
CAS
DRAMW
CSR 1.5 CLK
t
CNRN
t
CNRN
= RCD + RSH -1.5 CLK
RP
where
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
---------------0
NORMAL OR MASTER RESET:
DRAM Controller Address Register(DCAR)
Address MBAR + $4C (Bank0)
Address MBAR + $58 (Bank1)
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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