Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-59
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address bits as $0. In order for a bank to be accessible to an
external master, the address bits that are unavailable to the
external master must either be set to 0 in the DCAR or be
masked in the DCMR.
11.4.2.4 DRAM CONTROLLER MASK REGISTER (DCMR0 - DCMR1). Each DCMR
holds the address mask for each of the DRAM banks as well the definition of which types
of transfers are allowed for the DRAM banks. Each DCMR is a 32-bit read/write control
register. All bits in DCMR0 - DCMR1 are unaffected by either Master Reset or normal
reset.
BAM [31:17] - Base Address Mask
This field defines the DRAM address space through the use of address mask bits. Any bit
set to 1 masks the corresponding base address register (DCAR) bit (the base address bit
becomes a ‘‘don’t care’’ in the address comparison). Unmasked base address bits are
compared to the ColdFire core or external master transfer address to determine if the
transfer is accessing a DRAM address space.
0 = Corresponding address bit is used in DRAM bank decode
1 = Corresponding address bit is a ‘‘don’t care’’ in DRAM bank decode
SC, SD, UC, UD - Supervisor Code, Supervisor Data, User Code, User Data Transfer
Mask
This field masks allows specific types of transfers to be inhibited from accessing the
DRAM bank. If a transfer mask bit is cleared, a transfer of that type can access the
corresponding DRAM bank. If a transfer mask bit is set to 1, an transfer of that type can
not access the corresponding DRAM bank. The transfer mask bits are:
SC = Supervisor Code mask
SD = Supervisor Data mask
UC = User Code mask
UD = User Data mask
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 -
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
---------------0
NORMAL OR MASTER RESET:
-----------SCSDUCUD-
1514131211109876543210
00000000 00 0----0
NORMAL OR MASTER RESET:
DRAM Controller Mask Register(DCMR)
Address MBAR + $50 (Bank 0)
Address MBAR + $5C (Bank 1)
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Freescale Semiconductor, Inc.
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